Last Updated: February 2026 | Reading Time: 14 minutes
A capacitor on a schematic is an ideal component. A capacitor on a PCB is not. The moment you place a capacitor on a board and route traces to it, you introduce parasitic inductance, parasitic resistance, and coupling paths that can completely undermine the capacitor's intended function. A 100 nF bypass capacitor placed 15 mm from an IC power pin with thin traces and vias can be less effective than a 10 nF capacitor placed 2 mm away with proper routing. Layout determines performance more than component selection in many high-frequency and power integrity applications.
This guide covers the critical layout practices for capacitor placement on PCBs --- from bypass and decoupling capacitor positioning to via strategies, trace routing, multi-capacitor filtering, and EMI/EMC considerations. Whether you are designing a high-speed digital board, a switch-mode power supply, or an RF front end, these principles apply.
Every PCB trace and via has inductance. A typical PCB trace has approximately 1 nH per millimeter of length, and a standard through-hole via adds 0.5-1.5 nH depending on board thickness and pad geometry. This parasitic inductance, combined with the capacitor's own equivalent series inductance (ESL), forms a series inductance that limits the capacitor's effectiveness at high frequencies.
The impedance of a series inductor is:
Z_L = 2 * pi * f * L
Example: 5 nH of total parasitic inductance
At 10 MHz: Z = 0.31 ohms
At 100 MHz: Z = 3.14 ohms
At 1 GHz: Z = 31.4 ohms
Above the capacitor's self-resonant frequency (SRF), the parasitic inductance dominates and the component behaves as an inductor, not a capacitor. Every nanohenry of trace inductance you add lowers the SRF and increases impedance at high frequencies.
The current loop formed by the capacitor, its traces, the IC power pins, and the return path through the ground plane creates a radiating antenna. The radiated emissions are proportional to loop area and frequency squared:
E_radiated proportional to f^2 * A * I
Where:
f = frequency
A = loop area
I = current
Reducing the loop area between a bypass capacitor and its IC is the single most effective layout technique for reducing conducted and radiated EMI. A factor-of-two reduction in loop area reduces radiated emissions by 6 dB.
The most critical rule in capacitor placement is minimizing the distance between bypass/decoupling capacitors and the IC power pins they serve. Every millimeter of trace adds approximately 1 nH of inductance.
Target distances:
| Application | Maximum Distance | Notes |
|---|
| High-speed digital (> 100 MHz clock) | 1-3 mm | Closer is always better |
| General digital logic | 3-5 mm | Acceptable for < 50 MHz systems |
| Microcontroller, mixed-signal | 2-4 mm | Analog supply pins need the closest placement |
| FPGA / high-pin-count IC | 0-2 mm | Often requires via-in-pad or back-side placement |
| RF / microwave | < 1 mm | Component-to-pad distance is critical |
Practical technique: Place bypass capacitors before routing any other traces. They are the highest-priority components on the board after the IC itself. If you route signal traces first and then try to fit bypass capacitors into remaining space, the result is always a compromise.
Route the capacitor to the closest VCC and GND pins on the IC, not to distant pins or to the bulk power rail. The goal is to create the shortest possible current loop between the capacitor and the switching transistors inside the IC.
For BGA packages, this often means placing capacitors on the back side of the PCB directly underneath the IC, with vias connecting to the power and ground balls above.
A common mistake is routing a short, wide trace from the capacitor to the IC's VCC pin while allowing the ground return to flow through a long path in the ground plane. The total loop inductance includes both the power trace and the ground return path. Use a continuous ground plane directly beneath the capacitor and IC to minimize ground return inductance.
Via-in-pad places the via directly in the capacitor landing pad. This eliminates the trace segment between the pad and the via, removing 1-3 mm of trace inductance. It is the lowest-inductance connection method available.
Advantages:
- Minimum parasitic inductance (< 0.5 nH per connection)
- Smallest footprint on the component side
- Ideal for BGA fan-out with back-side capacitors
Requirements:
- Vias must be filled and planarized (copper-filled or epoxy-filled) to create a flat surface for SMD soldering
- Unfilled via-in-pad causes solder to wick into the via during reflow, creating a void or tombstone
- Adds fabrication cost (typically $0.02-0.05 per via for filling)
When via-in-pad is not practical (cost, fabrication capability), place vias as close to the capacitor pads as possible, using the shortest trace segments to connect pad to via.
Best practice: Place vias within 0.5 mm of the pad edge, on the side of the pad closest to the IC. Avoid routing long traces from the pad to a distant via.
Via stitching connects ground planes on multiple layers with a grid of vias. Around bypass capacitors, via stitching reduces the ground plane impedance and provides a low-inductance return path for high-frequency currents.
Recommendation: Place ground stitching vias around every bypass capacitor cluster and around the perimeter of ICs. Spacing of 3-5 mm between stitching vias is typical for digital boards; 1-2 mm for RF.
Power traces to capacitors should be as wide as practical. Trace inductance decreases with increasing width:
L_trace (nH) approximately = 5.08 * h * ln(2 * l / (w + t))
Where:
h = height above ground plane (mm)
l = trace length (mm)
w = trace width (mm)
t = trace thickness (mm)
Practical guidelines:
| Power Current | Minimum Trace Width | Recommended Trace Width |
|---|
| < 500 mA (logic IC) | 0.25 mm (10 mil) | 0.5 mm (20 mil) |
| 500 mA - 2A (processor) | 0.5 mm | 1.0 mm (40 mil) |
| 2-10A (power converter) | 1.0 mm | 2.0-5.0 mm |
| > 10A (motor drive, power stage) | Copper pour / bus bar | Full plane layer |
A continuous, unbroken ground plane on the layer immediately adjacent to the component layer is the most effective ground strategy. This plane provides:
- Low-inductance return path for all bypass capacitor currents
- Shielding between signal layers
- Thermal spreading for power dissipation
Critical rule: Never route signal traces that cut across the ground plane beneath a bypass capacitor. Cuts in the ground plane force return currents to flow around the cut, dramatically increasing loop area and inductance.
For two-terminal MLCCs, orient the capacitor so current flows through the shortest dimension. Standard 0402 and 0201 MLCCs have lower ESL when current flows along the length (long-axis mounting). However, reverse-geometry capacitors (such as 0306 instead of 0603) have significantly lower ESL because the current path through the capacitor's internal plates is shorter.
ESL comparison:
| Package | Standard Orientation ESL | Reverse Geometry ESL |
|---|
| 0603 | ~0.7 nH | 0306: ~0.3 nH |
| 0402 | ~0.5 nH | 0204: ~0.2 nH |
| 0805 | ~1.0 nH | 0508: ~0.4 nH |
For applications above 500 MHz, consider specialized low-inductance capacitor packages:
- Reverse-geometry MLCCs (e.g., AVX, TDK low-ESL series): 0.2-0.4 nH ESL
- Interdigitated capacitors (IDC): multiple internal terminations, ESL < 0.1 nH
- Land grid array (LGA) capacitors: four or more terminals, ESL < 0.05 nH
- Three-terminal feedthrough capacitors: provide additional filtering, ESL < 0.1 nH
For high-speed digital and RF boards, use a stack-up that places the ground plane directly adjacent to the component layer (Layer 1: components/signals, Layer 2: ground plane). This minimizes the height of the current loop and reduces inductance proportionally.
A single capacitor provides low impedance only near its self-resonant frequency. Below the SRF, impedance is capacitive and drops with frequency. Above the SRF, impedance is inductive and rises with frequency. To achieve low impedance across a broad frequency range, you need multiple capacitors with staggered SRFs.
| Stage | Capacitor Value | Package | SRF Range | Function |
|---|
| Bulk | 10-100 uF | Electrolytic or large ceramic | 10 kHz - 1 MHz | Energy storage, low-frequency decoupling |
| Mid-frequency | 100 nF - 1 uF | 0805 or 0603 MLCC | 1-30 MHz | Mid-frequency decoupling |
| High-frequency | 1 nF - 10 nF | 0402 or 0201 MLCC | 50-500 MHz | High-frequency noise filtering |
Placement priority: The high-frequency capacitors must be closest to the IC. The bulk capacitor can be farther away (10-20 mm is acceptable) because it only needs to supply current at lower frequencies where trace inductance is less significant.
When two capacitors with different SRFs are connected in parallel, an anti-resonance peak occurs between their SRFs. At this frequency, the impedance can be higher than either capacitor alone. The peak magnitude depends on the ESR of both capacitors --- higher ESR damps the anti-resonance.
Mitigation strategies:
- Use capacitors with overlapping impedance curves (don't skip decades in value)
- Place a medium-value capacitor between the bulk and high-frequency values
- Accept that some anti-resonance is inevitable; keep the peaks below the target impedance
- Use simulation tools (such as Keysight ADS, Ansys SIwave, or free tools like the Murata SimSurfing) to model the combined impedance
X capacitors (line-to-line) and Y capacitors (line-to-earth) have specific placement requirements beyond normal bypass capacitor rules:
X capacitors:
- Place directly at the AC mains input, before any other filtering components
- Keep traces short and wide to minimize inductance that would reduce filter effectiveness
- Ensure discharge resistors are connected directly across the X capacitor (required by safety standards --- the capacitor must discharge to safe voltage within 1 second after unplugging)
Y capacitors:
- Place as close to the transformer or isolation barrier as possible
- Route traces to respect creepage and clearance distances between primary and secondary circuits
- Ensure trace routing does not create additional coupling paths that would increase leakage current beyond safety limits (0.5 mA for medical, 3.5 mA for IT equipment)
In a typical EMI filter (common-mode choke + Y capacitors + X capacitor), the physical order matters:
- AC inlet connector
- Fuse
- X capacitor (differential mode filtering)
- Common-mode choke
- Y capacitors (common-mode filtering, tied to chassis ground)
- Second X capacitor (optional, additional differential filtering)
Route the filter components in a linear flow from input to output. Avoid routing the filtered output traces near the unfiltered input --- coupling between input and output defeats the filter.
The most common mistake. A 10 mm trace from a bypass capacitor to an IC power pin adds approximately 10 nH of inductance, making the capacitor ineffective above 20-50 MHz.
Signal traces that cut across the ground plane beneath a bypass capacitor disrupt the ground return path and increase loop area. Keep the ground plane solid in the entire area between bypass capacitors and their ICs.
Each bypass capacitor should have its own dedicated via pair to the power and ground planes. Sharing a via between two capacitors forces their return currents through a common inductance, creating coupling and reducing effectiveness.
The opposite of correct priority. Small high-frequency MLCCs need to be closest to the IC. Large bulk capacitors can be farther away because they serve low-frequency energy demands where trace inductance is less critical.
Placing electrolytic capacitors next to hot components (voltage regulators, power MOSFETs, braking resistors) accelerates electrolyte evaporation. Every 10 degrees C increase in operating temperature halves the capacitor's life. Position electrolytics in the coolest area of the board that still maintains acceptable electrical performance.
Mistake 6: Inadequate Creepage on High-Voltage Capacitors#
Film and electrolytic capacitors rated for hundreds of volts need adequate PCB trace spacing. A 400V DC bus capacitor with 0.5 mm trace spacing will eventually arc, track, and fail. Follow IPC-2221B Table 6.1 for minimum conductor spacing at your operating voltage.
For general digital circuits operating below 50 MHz, 3-5 mm is acceptable. For high-speed digital circuits (100 MHz+ clock rates), target 1-3 mm. For FPGAs and processors with fast edge rates, bypass capacitors should be directly adjacent to or underneath the package using via-in-pad connections. The critical metric is total parasitic inductance (trace + via + ESL), not just physical distance. A 3 mm trace with a via-in-pad connection may have lower total inductance than a 1 mm trace that routes through a long via stub.
Placing bypass capacitors on the back side of the board (opposite the IC) is an excellent technique for BGAs and other high-pin-count packages. The capacitor connects through short vias directly to the power and ground planes, which then connect to the IC's power balls through additional vias. The total loop inductance can actually be lower than a component-side placement with long traces, because the via connections are very short and the plane layers provide an extremely low-impedance connection. The key requirement is that the power and ground planes are on adjacent layers with minimal separation.
This depends on the IC's transient current demands and operating frequency. A general guideline is one bypass capacitor per VCC/GND pin pair. For microcontrollers with 2-4 power pin pairs, use 2-4 bypass capacitors (typically 100 nF each) plus one bulk capacitor (10 uF). For FPGAs with 20-100+ power pin pairs, each power pin pair gets its own bypass capacitor, plus distributed bulk capacitance. Always check the IC manufacturer's reference design and layout guidelines --- they have characterized the specific decoupling requirements for their devices.
Multiple small capacitors in parallel are superior to a single large capacitor for high-frequency decoupling. Parallel capacitors divide the ESL by the number of capacitors (two 100 nF in parallel have half the ESL of one 100 nF), extending the useful frequency range. They also share ripple current, reducing thermal stress on each individual capacitor. For bulk energy storage at low frequencies, a single larger capacitor is acceptable. The optimal strategy is to combine both: distributed small MLCCs for high-frequency decoupling and fewer large capacitors for energy storage.
Via-in-pad is a fabrication technique where a via is drilled directly in the component landing pad, then filled with copper or epoxy and planarized to create a flat surface for SMD soldering. It eliminates the trace segment between the pad and the via, typically saving 1-3 nH of parasitic inductance per connection. Via-in-pad is worth the extra cost (typically $0.02-0.05 per via in production) when operating above 100 MHz, when board space is severely constrained (such as BGA fan-out), or when every fraction of a nanohenry matters for power integrity. For boards operating below 50 MHz or with relaxed EMI requirements, standard via-adjacent routing is usually sufficient.
